1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly relates to a semiconductor device including bit lines that are hierarchically structured.
2. Description of Related Art
Many of semiconductor memory devices as represented by a DRAM (Dynamic Random Access Memory) have a plurality of word lines extending in a row direction and a plurality of bit lines extending in a column direction. A plurality of memory cells are arranged at intersections between the word lines and the bit lines. When one of the word lines is selected, memory cells allocated to the selected word line are electrically connected to corresponding bit lines and then data held in the memory cells are readout to the bit lines. The read data are amplified by sense amplifiers connected to the bit lines, respectively.
However, with the configuration mentioned above, one sense amplifier needs to be provided for each bit line or each pair of bit lines and thus many sense amplifiers are required. As a method to solve this problem, a semiconductor memory device using bit lines that are hierarchically structured is proposed (see Japanese Patent Application Laid-open No. 2009-271985).
The semiconductor memory device described in Japanese Patent Application Laid-open No. 2009-271985 includes local bit lines each connected to memory cells and global bit lines each connected to a sense amplifier. A plurality of local bit lines are allocated to one global bit line to reduce the number of required sense amplifiers.
However, in the semiconductor memory device described in Japanese Patent Application Laid-open No. 2009-271985, switch circuits that connect the global bit line and the local bit line are configured to be turned on simultaneously with activation of a corresponding word line. As a result, the local bit line is connected to the global bit line before data is sufficiently read out to the local bit line. Thus, for example, when the global bit line receives noise from another adjacent global bit line, data is adversely inverted. Such a problem occurs not only in semiconductor memory devices such as a DRAM but also in all semiconductor devices including bit lines that are hierarchically structured.